1. Field of the Invention
Embodiments of the present invention relate generally to digital designs and more specifically to a method and system for placing multiple loads in a high-speed system.
2. Description of the Related Art
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A printed circuit board (“PCB”) is commonly used to provide a mechanical structure on which discrete electronic components, such as integrated circuits, resistors, capacitors and the like, are mounted and interconnected. The interconnections in a PCB are provided by layers of patterned traces of metal, typically copper, on and in the PCB. Each of these interconnections has a device that is changing the state, or the signal, on the interconnection, herein referred to as a driver, and a device that is reading the signal from the interconnection, herein referred to as a receiver or a load. In high-speed system designs, instead of modeling the behavior of the interconnections as lumped capacitors or simple delay lines, the interconnections are modeled as transmission lines to properly characterize the timing issues associated with the decreasing timing budgets allotted for the interconnections.
Some of the issues relating to signal integrity in high-speed system designs include the reflections along the interconnections and the noises associated with power distribution. To illustrate, FIG. 1A and FIG. 1B are simplified layouts of printed circuit boards with multi-loads in high-speed systems. Specifically, the system In FIG. 1A, 100, includes PCB 102, driver 108, load a 104, and load b 106. Signal pin 122 of driver 108, signal pin 112 of load a 104, and signal pin 118 of load b 106 are connected to trace 124. Driver 108 drives a signal, Vinitial, via signal pin 122 onto trace 124, and the signal propagates towards the two loads. Because of the split at T-point 126 and the daisy-chaining of load a 104 and load b 106, the integrity of the signal on trace 124, especially the signal arriving at signal pin 118, is negatively impacted. In particular, since trace 124 in effect terminates at load a 104, which most likely does not have the matching characteristic impedance of trace 124, a portion of Vinitial, also referred to as Vreflected, reflects back down trace 124 toward driver 108. Then driver 108 may reflect yet another portion of Vreflected back toward load a 104. This reflecting and counter-reflecting process generally continues until steady state is reached on trace 124. Because these initial, reflected, and counter-reflected signals all travel on the same path and interfere with one another, the integrity of the intended signal on trace 124, Vinitial, is severely degraded.
Unlike the placement of the loads illustrated in FIG. 1A, in FIG.1 B, load c 154 and load d 156 are placed on both sides of PCB 152 in system 150. Although the physical distance between these two loads may be shorter than the distance between load a 104 and load b 106 shown in FIG. 1A, system 150 is still subject to various signal integrity problems. In particular, the introduction of stubs 178 and 180, which respectively connecting signal pin 162 of load c 154 and signal pin 168 of load d 156 to T-point 176 via paths of some lengths, causes non-uniformity of the characteristic impedance of trace 174. This in turn negatively impacted the integrity of the signal traveling on trace 174. In addition, the aforementioned reflection problem also exists in this system, because the impedance of the terminating load c 154 and load d 156 is unlikely to match the impedance of trace 174, which may be non-uniformed as mentioned above. Furthermore, because decoupling capacitors 164 and 170 are positioned away from power pins 160 and 166, respectively, the intended effect of the decoupling capacitance to reduce noise in the power distribution of PCB 152 is significantly diminished.
As the foregoing illustrates, what is needed is a way to place multiple loads in a high-speed system so that the signal integrity of the system is maintained.